Automated test equipment (ATE) is used to test integrated circuits (ICs) after they have been manufactured. In order to test a particular IC, the ATE is interfaced with the pins of the IC by interfacing logic, which typically comprises one or more printed circuit boards (PCBs). The integrated circuit being tested typically is referred to as the “device under test” (DUT) and the interfacing logic typically is referred to as the DUT interface. Because the DUT interface typically comprises one or more PCBs, the DUT interface is commonly referred to as the “DUT boards”.
FIG. 1A illustrates a typical test system 75 for testing an integrated circuit 101. The system 75 includes a DUT interface 100 and ATE 105. The ATE 105 comprises a device tester 110. The DUT interface 100 generally is configured to connect each port of the IC 101 to respective input/outputs on the device tester 110 of the ATE 105.
In this example, IC 101, which corresponds to the DUT, includes input/output ports 120-127. The ports 120-127 of IC 105 are connected to device tester 110 via test interface 100. It can be seen that the test interface 100 comprises interconnects A-H, each of which is electrically connected to a respective port of the IC 101. These interconnects A-H are connected by respective conductors 150 to interface outputs A_-H_, respectively. Each interface output A_-H_ is directly connected to a respective input of the device tester 110.
During a test mode, the device tester 110 outputs stimulus data (i.e., one or more sets of test vectors) that is fed to the IC 101. The device tester 110 also receives response data from the IC 101 via the test interface 100. Based upon the response data received for given stimulus data, the operation/functionality of the IC 101 can be evaluated.
An IC design may also be evaluated before fabrication of an actual IC having the design by creating a software model of the IC and then processing the model. One manifestation of a software model of an IC is a structural netlist. For example, an IC may be represented by a Verilog or VHDL gate level netlist. As is well known to those skilled in the art, such an IC model may be provided as input to an automated test pattern generator (ATPG), which can generate a set of test patterns. Examples of ATPGs that are currently available are Synopsys TetraMax and Mentor Graphics Fastscan. The test patterns can be represented as stimulus and expected response data in languages such as Verilog or VHDL, for example. The test patterns and model can be processed by a simulator such as, for example, an NC-Verilog simulator or a VCS simulator, and the simulation results can be checked for correctness.
FIG. 1B shows a block diagram of a model 175 that is representative of an IC 101. The data structure representing the model 175 of the IC 101 is input to a simulator 176, which is a software program being executed on a computer (not shown) of suitable type. The simulator 176 also receives a test pattern set 178 that has been generated by an automatic test pattern generator (ATPG) 177. The test pattern set 178 includes test patterns and expected responses to the test patterns. The ATPG 177 also receives the IC model 175 and uses it to generate the test pattern set that is subsequently used by the simulator 176. The simulator 176 simulates operation of the IC 175 by running the model and tests of the model of the IC 175 with the test pattern set 178. The simulator 176 typically is used to test a design of an IC prior to the IC being fabricated to ensure the correctness of the design. The ATPG 177 utilizes the IC model 175 to generate the test pattern set 178. The ATPG 177 typically also is a software program being executed by a computer of some type.
The test pattern set 178 may be translated (not shown) and provided to the ATE 179, which is used to test an IC that has actually been fabricated. The ATE 179, when interfaced to a DUT via a DUT interface, such as that shown in FIG. 1A, tests and evaluates the DUT by outputting test patterns to the DUT and evaluating the results returned to the ATE.
During testing, the ATE utilizes test patterns that were generated by the ATPG in the aforementioned manner. The test patterns, also known as test vectors, comprise a series of logic 1s and 0s. In response to a given test pattern being input to the DUT, the DUT will produce a pattern of 1s and 0s that are output from the DUT to the ATE via the DUT interface. For each test pattern generated by the ATE, the ATE knows how the DUT should respond based on the model of the DUT. Therefore, for any given test pattern, the ATE can determine, based on the output received from the DUT via the DUT interface, whether a fault has occurred.
This known method of evaluating an IC design by modeling the IC generally works well as long as the IC being modeled has no more input/output ports than the device tester 110 (FIG. 1A) can be configured to accommodate. However, over the course of the past few years, the number of gates included in typical ICs has increased exponentially. Furthermore, as ICs have been fabricated to include more gates, the number of input/output ports necessary to interface the IC with external hardware/circuitry has also increased. Unfortunately, tester devices generally have not developed as quickly as IC designs. As a result, there are cases where tester devices are not equipped with enough inputs/outputs to provide for a direct connection with each and every input/output port of the IC. In such cases, it may not be possible to use such a tester device to directly evaluate the signal(s) on each and every input/output port of the IC.
Despite these changes in IC design complexity and limitations associated with some ATE configurations, the DUT interface is not taken into account in models used for IC testing. A need exists for a system for evaluating ICs that takes into account constraints that are placed on the inputs and outputs of the IC by the DUT interface logic.